This invention relates generally to the use of cache memories as part of data processors, and, more specifically, to techniques of generating addresses to fetch instruction data from a cache memory.
Cache memories are used in data processors of various designs to improve the speed with which frequently used data is accessed. A single cache is often utilized for both instruction and user data but separate instruction and data caches are more commonly used in high performance processors. Cache memory is typically integrated with a microprocessor on a single chip. The limited capacity cache memory of a processor is loaded from a main system memory as necessary to make the frequently used data available for fast access by the processor. If data at a particular memory address specified by the processor is not in the cache, a significant number of processing cycles is required to obtain the data from the main memory and either write it into the cache or provide it directly to the processor, or both.
Addresses of instruction data are typically generated in a pipeline having at least two stages, one to calculate an address in one operating cycle and the next to apply that calculated address to the cache in the next operating cycle. Also during the second operating cycle, any data in the cache at that address is typically read out and written to an instruction buffer, and a status signal is returned to indicate whether data is present at that address or not, in terms of a "hit" or "miss." If a miss, the cache accesses main memory to obtain the data at that address, typically resulting in a delay of many operating cycles before the data becomes available for writing into the instruction buffer. If a hit, it is desired to generate the next address as quickly as possible from the hit address plus the amount of data being returned from the cache at the hit address, preferably in the second operating cycle, in order to minimize the number of operating cycles required generate each address. However, it is difficult to resolve in the second cycle whether the current address has resulted in a hit or miss, in time to be used to generate the next address in the second cycle, resulting in either lengthening the duration of the cycles or waiting until the next cycle after the hit signal is returned in order to generate the next address. The performance of pipelined and other types of processors is adversely affected by such delays.
Therefore, it is a general object of the present invention to provide improved instruction fetch techniques that minimize the number of operating cycles required to address the cache and read instruction data from it.
It is a more specific object of the present invention to improve the speed at which instruction data at an address for which a miss signal is returned is accessed for use by the processor.